Energy Efficient and Reliable Embedded Nanoscale SRAM Design

Continuing progress and integration levels in silicon technologies make possible complete end-user systems consisting of multicores on a single chip targeting either embedded or high-performance computing. To relentlessly meet this ubiquitous need recently evolved multicore architectures need large, embedded memories to support high bandwidth and computational requirements. Therefore, for the foreseeable future, static random-access memory (SRAM) will likely remain the embedded memory technology of choice for many microprocessors and systems on chips
(SoCs) due to its speed and compatibility with standard logic processes. For these reasons, it is considered to be highly promising and attracted considerable research attention toward optimizing its reliability, power, and speed.
Consequently, designing energy-effciency SRAMs is one of the key components for energy-effcient systems. However, without new paradigms of energy-effcient designs, producing embedded SRAM capable of meeting the computing storage and communication demands of the emerging applications will be unlikely.